Vector display system

ABSTRACT

A vector display system is disclosed for use with CRT and similar devices which display a line in a coordinate system. A ramp voltage is multiplied by scaled departure components Delta X and Delta Y to assure straight lines, and the ramp rate is selected by an approximation of the line length computed digitally. The ramp voltage is backed up to initially deflect the beam in the opposite direction before ramp generation is initiated and video is turned on. The video-on and video-off times are delayed by constant amounts to allow for lag of the beam deflection system behind the beam deflection signals generated from the sum of analog signals representing present position, and the product of departure data and the ramp voltage. Video turn off is initiated when the ramp voltage crosses a reference which is scaled by the reciprocal of the scaling factor used for the components Delta X and Delta Y.

United States Patent Inventors Robert W. Waller Northridge; James F.Gruder, Manhattan Beach, both of, Calif. [2H Appl. No. 841,705 [22]Filed July 15, I969 [45] Patented June I, 9171 [73] Assignee InformationInternational, Inc.

Boston, Mass.

[54] VECTOR DISPLAY SYSTEM 11 Claims, 4 Drawing Figs.

[52] U.S.Cl 315/18 H0lj 29/70 [50] Field of Search 3l5/l8 [56]References Cited UNITED STATES PATENTS 3,320,409 5/l967 Larrowe 315/18VGT SCALED DIGITAL COMP.

VIZ ANAL COMP.

BEAM CONT LTF-IN2 DIGITAL COMB 3,510,865 5/]970 Callahan etal.

ABSTRACT: A vector display system is disclosed for use with CRT andsimilar devices which display a line in a coordinate system. A rampvoltage is multiplied by scaled departure components AX and AY to assurestraight lines, and the ramp rate is selected by an approximation of theline length computed digitally. The ramp voltage is backed up toinitially deflect the beam in the opposite direction before rampgeneration is initiated and video is turned on. The video-on andvideo-off times are delayed by constant amounts to allow for lag of thebeam deflection system behind the beam deflection signals generated fromthe sum of analog signals representing present position, and the productof departure data and the ramp voltage. Video turn off is initiated whenthe ramp voltage crosses a reference which is scaled by the reciprocalof the scaling factor used for the components AX and AY.

PATENTED JUN H97! 582,705

' sum 1 or 4 NDX NDY 2 2 VGT VGT M SCALED AX SCALED AY MDA AX-REG.AY-REG DIGITAL COMP;

DIGITAL COMFZ GT E YGX GTF LTF

RAMP

VO LTAG GEN.

BEAM VIZ ANA CONTR COME GTE-I GTF-IN1 LTF'IN2 INVIz'N'l'OR. ROBERT W. WAF I 1 BY JAMES F. GRUDER Mal/ 3 haim),

ATTORNEYS PATENTED JUN H9?! $582,705

sum 2 OF 4 INVIEN'I'OR. ROBERT w. WALLEH JAMES F. GRUDER-" ii: Pm AVG FG i i v R a mOhQmmZmO midi ATTORNE Y PATENTE'D I B71 SHEET 5 BF 4 STARTVGT GTE-INO VIZ LVD

GTF'IN1 LTF-IN2 SET TVD

VIDD

RESET VIDD FIG. 4

INVHN'I'ORS ROBERT W. WALLER JAMES F GRU DER wcwb a 4' ATTORNEYSBACKGROUND OF THE INVENTION This invention relates to systems for thevisual display of data, and more particularly to a cathode-ray tube(CRT) system for displaying straight lines defined by digital input datain a conventional rectangular coordinate system.

At least one general function to be performed by apparatus of thepresent invention is to electronically display straight lines by storingrectangular (X,Y) coordinate data in digital form, and multiplying alinear ramp voltage that increases from zero to a reference level by thestored data to obtain deflection signals which move the beam from itspresent position to a new position as specified by the coordinate data.Once the end point is reached, the present position data is updated tocomplete a line display cycle. Another cycle can be initiated aftersufficient time has elapsed for the CRT circuits to settle at the newposition.

The ramp voltage, multiplied by numbers proportional to AX and AY,controls the velocity at which the beam is deflected with respect toeach axis from its present position to its new position. By using thesame ramp voltage for both the X and Y axis, the correct relationship ismaintained in the position and velocity of the beam as it is deflectedin each axis from the present to the new position so that the beamarrives at the end point of each axis at the same time, i.e. so that itmoves to its new position in a straight line. However, since theapparent intensity of a CRT display is inversely proportional to thevectorial velocity at which the beam transverses the face of the CRT,that velocity must be controlled for all line lengths (i.e. vector sumsof AX and AY components). That is accomplished by so controlling theramp voltage rate that the vectorial velocity of the line will beconstant. Then the electron beam intensity need not be controlled tomaintain line intensity constant.

A direct approach to beam velocity problems is to simply make the ramprate inversely proportional to the length of the line being drawn bycomputing the reciprocal of the square root of the sum AX AY, andcontrolling ramp rate as a function of the square root. However, themechanization of a square root computer is complex, and the requiredvariation in ramp rate is so large that the total system speed would beseriously limited.

With the beam velocity maintained constant, the only control on the beamintensity required is an unblanking signal to turn it on when generationof the ramp voltage is initiated, and to turn it off when the rampvoltage has reached a predetermined reference level. That referencelevel remains the same while the ramp rate is being varied to achieveconstant beam velocity.

If a high ramp rate is applied to the deflection system, the electronbeam position will lag the deflection signals by a fixed time,particularly in CRTs having magnetic deflection systems, and it willtake some time before the beam velocity is equal that called for by theramp rate. While the fixed time error may be handled by delaying theturn-on and turn-off times of the electron beam by a constant amount,the initial difference in velocity presents a more difficult problemsince the slower velocity at the beginning will cause greater lineintensity, thereby producing teardropping and bending of the line at thestart.

While systems have been devised which deal with some of these problemsof displaying straight lines between two points on the face of a CRT,such as a system disclosed in US. Pat. No. 3,320,409 granted May 16,1967 to B. T. Larrowe, the efficiency and effectiveness of solutionshave in the past left much to be desired. Accordingly, an object of thepresent invention is to provide more efficient and effective CRT systemfor displaying straight lines defined by digital input data in aconventional rectangular coordinate system.

SUMMARY OF THE INVENTION In accordance with the present invention,straight lines are displayed on a CRT by multiplying scaled rectangularcoordinate departure data (AX, AY) in digital form with a ramp voltagewhich starts slightly above or below zero (in the direction opposite tothe direction the line is to be drawn) through separate multiplyingdigital-to-analog converters (M DACs). A zero-level detector determineswhen the ramp voltage passes through zero volts and generates a video-onsignal. A delay circuit responds to the video-0n signal to turn on anunblanking signal generator (or turn off a blanking signal generator)after a fixed time delay. In the meantime, the outputs of the MDACs aresummed with corresponding outputs of digital-to-analog converters (DACs)which have as their inputs coordinate data (X,Y) of the starting pointfor the line to be drawn. Once the unblanking pulse is generated, thedesired trace is made on the CRT in a straight line without teardroppingor bending at the start. After the ramp voltage reaches a predeterminedlevel, a second level detector generates a video-off signal. A delaycircuit responds to the video-off signal to turn off the unblankingsignal generator after the same or greater fixed time delay as the delayintroduced in turning the unblanking signal generator on. This delay atturn-on and turn-off of video compensates for CRT beam lag in theresponse of its deflection system to the sum of the outputs of theassociated MDACs and DACs.

For substantially constant intensity of a line being displayed, the rampvoltage rate is selected to be inversely proportional to anapproximation of the length of the line to be displayed. Theapproximation is made by determining which departure component AX or AYis larger and forming a composite digital word of a predetermined numberof the most significant digits of the largest component L and apredetermined number of the most significant digits of the remainingcomponent S, and applying the composite LS to the ramp generator whichcomprises a constant current source driving a bank of integratingcapacitors selected by the composite LS. The capacitors are of differentsizes according to the weight of the component L digits and according toapproximately 0.375 of the weight of the component 5 digits, where themost significant digit of the component L sets the nominal size whichall other capacitors are scaled down.

This approximation method is more economical and efficient than tocompute the line length and control ramp rate to be inverselyproportional. However, it requires a very large range of ramp rates. Torelax the dynamic range requirements on analog circuits, the departurecomponents AX and A! are scaled upon transferring them into associatedMDACs. Then to terminate the line at the correct point, the level of theramp voltage at which the video is turned off is scaled correspondingly.Thus, if the components AX and AY are scaled up by multiplying by afactor N, the ramp termination voltage level is scaled down by dividingby a factor N.

Scaling of the components AX and AY is efficiently accomplished byeffectively shifting the components the necessary number of places atthe time of transfer to MDACs through gates effectively selected by thescaling factor employed. When scaling is used, control of the ramp rateis in accordance with the scaled departure components. In theapproximation technique referred to hereinbefore, that is mostefficiently accomplished by selecting L and S digits from the scaledcomponents in the MDACs.

The novel features that are considered characteristic of this inventionare set forth with particularity in the appended claims. The inventionwill best be understood from the following description when read inconnection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. ll illustrates an exemplaryarrangement for a preferred embodiment of the present invention.

FIG. 2 illustrates schematically an exemplary ramp generator for thearrangement of FIG. I.

FIG. 3 illustrates schematically an exemplary multiplyingdigital-to-analog converter for the arrangement of FIG. 1.

FIG. 4 illustrates schematically a video control network for thearrangement of FIG. 1.

DESCRIPTION OF PREFERRED EMBODIMENTS The techniques. and organization ofan exemplary system employing the techniques of the present invention.will now be described with reference to the drawings. However, althoughparticular implementations of various features will be suggested, itshould be understood that all of the features to be referred to may beimplemented in several different ways. The choice to be made for aparticular implementation of a given feature will depend upon theparticular environment and operating requirements of the CRT displaysystem employing 11.

Referring now to FIG. '1, the overall function of the present inventionis, as noted hereinbefore, to generate X and Y deflection signalsrequired to position the electron bema of a CRT. or similar displaydevice, to a specified position and generate AX and AY deflectionsignals and to generate video on and off signals to display a line fromthe present beam position to a new position. The system employing thepresent invention will have means for computing or receiving newposition coordinates, either in the absolute form as X and Y coordinatedata, or in a relative form as AX and AY departure data relative to thepresent position.

For simplicity in understanding the present invention, it is assumedthat new position coordinates are received in a relative form, such asfrom a digital computer, and stored in AX- and AY-registers 11 and 12while the present position is stored in X and Y registers 13 and 14. Itwill also be assumed that all values are binary expressed in signmagnitude" form with the origin of the coordinate system at the lowerleft corner of the CRT so that all present position data for points onthe face of the CRT will be positive while departure data may bepositive or negative, depending upon the direction ofthe line to bedisplayed.

For simple repositioning, new X and Y coordinate data are received inthe respective registers 13 and 14. The parallel outputs from thoseregisters are employed to drive conventional digital-to-analogconverters (DACs) 15 and 16. The outputs of the DACs are the respectiveX and Y deflection signals applied to the deflection system of the CRTvia respective summing amplifiers 17 and 18. A repositioning operationis considered complete after the DACs are updated and sufficient timehas elapsed for the CRT circuits to settle. The electron beam isdeflected as fast as the CRT circuits will allow. After the CRTs havesettled, a point can be plotted at the new position by turning the video(electron beam) on (having turned it off when deflection was initiated).oranother operation can be initiated.

For line drawing, it is necessary to control the manner in which thebeam is deflected (in response to departure data received by theregisters 11 and 12) in such a manner that the line will be straight andof uniform intensity. This requires so interpolating the rates of the Xand Y deflections that they will arrive at a point of completion at the'same time. If that is accomplished, the beam moves to its new positionin a straight line. After reaching the new position. the presentposition data are updated by adding the contents of the AX- andAY-registers to the contents of the X- and Y-registers. That may beaccomplished by counting the X- and Y-registers up, and down, dependingon the signs of the departure data as the AX- and AY-registers to thecontents of the X- and Y-registers. That may be accomplished by countingthe X- and Y-registers up, or down, depending on the signs of thedeparture data as the AX and AY-registers are decremented to zero.Suitable up-down counters are commercially available. Alternatively, allregisters may be provided as simply banks of, for example, D-typeflip-flops with updating accomplished through a bank of full adders.Either form ofimplementation is represented in FIG. 1 by updating busses19 and 20.

Effectively interpolating the rates of X and Y deflections isaccomplished by a ramp voltage generator 21 which transmits a rampsignal to multiplying digital'to-analog converters (MACS) 22 and 23which receive AX and AY data through scaling gates where they aremultiplied by. for example I. 8 or 64 according to the criteria setforth in the following table.

Criteria Mult. Control lAXI or [AYl2200la 1 GTE IAXI and lAY| 200l andIAXl or |AYl 017la 8 GTE -lAX[ and IAY $017!; 64 LTF The result of thisscaling operation is that the digital input of at least one of the MDACswill be2 'i200,,, where the subscript indicates a binary numberexpressed in octal form. A digital comparator network 25 receives the AXand AY data (without signs) and generates the control signals GTE, GTFand LTF.

The network 25 may be comprised of four static comparators for makingthe decisions AX 200[,,, AY 2OOI AX Ol7| and AY Ol7| to provide signalsA, B, C and D respectively. Logic gates may then form the scaling factorcontrol signals according to the following logic equations:

The reason for scaling is to relax the ramp rate range of the rampgenerator 21 which is employed to so vary ramp rate as to maintain thebeam velocity constant. For constant beam velocity without scaling, itwould be necessary to make the ramp rate inversely proportional to thelength of the line being drawn according to the following equation:

1 Ramp Rate: 7 720+ Y2 That would require a very large range of ramprates (about 140011 for l0 bit numbers exclusive of the sign). Scalingreduces the ramp rate range to abut 10: I.

As noted hereinbefore, the actual ramp rate used for given components AXand AY is inversely proportional to the largest component plusthree-tenth to four-tenth the smallest component. When the componentshave been scaled, the scaled values are used for the ramp rateselection. Accordingly, the MDACs are provided with storage registerswhich can provide the scaled AX and AY values. To determine which isgreater, the most significant 4bits of the MDAC registers are comparedin a digital comparator 26, and if the scaled AX is greater than thescaled AY, a signal on a line XGY gates the five most significant digitsMX to MX of the scaled AX into the ramp generator 21 from the MDAC 22 asthe L-digits and gates the four most significant digits MY to MY ,ofscaled AY into the ramp generator 21 from the MDAC 23 as the S-digits toform the composite which make up the approximation of the length of theline, but scaled to relax the dynamic range requirements of the analogcircuits which process the ramp voltage. Conversely, if the scaled AY isdetermined to be greater than scaled AX, a signal on a line YGX gatesdigits from the MDACs 23 and 22 into the ramp generator 21 as therespective L and S digits. The L and 5 digits select integratingcapacitors in the ramp generator 21.

In a preferred embodiment of the ramp generator 21 shown in FIG. 2, theL and 5 digits are entered through groups of selecting gates, such asgates 24, in response to XGY and YGX signals. The ramp generator itselfcomprises a plurality of capacitors, such as capacitor 27, a pluralityof switches responsive to the L and S digits, such as a switch 28, aconstant current source 29, and a shunt switch 30. Each switch, such asswitch 30, consists of an NPN transistor Q and a bias network whichturns the transistor on in response to a positive input signal. In thecase of the switch 30, the input signal W is positive until rampgeneration is initiated, thereby shunting current from the source 29 toground. In the case of the other switches, the L and S digit signals arepositive when equal to binary l to turn on the switch and therebyconnect an associated capacitor to ground.

The capacitors selected by the L digits L to L and the S digits S to S,are weighted in accordance with the binary weight of the digits in eachgroup. Thus, for the L digits, the capacitors selected by digits L to Lweighted 2 C, 2 C, 2 C, 2C and 2"C while the capacitors selected bydigits S to S, are weighted KZC, K C, K2 C and K2C, where C is aconstant such as 8,000 picofarads, and K is a constant equal to about0.35. When selected capacitors are connected in parallel between theoutput of the current source 29 and ground, their capacitances are addedso that the ramp rate can be said to be inversely proportional to theweighted sum of the L digits plus 0.35 times the weighted sum of the Sdigits. This relationship can be conveniently expressed as ramp rateRR=l/L+0.35S where L +0.35S is an approximation of the line length.

The selection of the capacitors is made before a signal VIP is set true(positive), at which time the complementary signal VIP goes to zero toturn off the switch 30. The voltage output of the capacitors thenincreases at a rate inversely proportional to the line length.

The ramp voltage from the capacitors in the ramp generator 25 isconnected to an emitter follower circuit 31 comprising two cascadedtransistors Q and 0;. However, the ramp voltage is not applied to thedeflection system through the summing amplifiers 17 and 18 until aflip-flop VGT (FIG. 4) is set. At this time the deflection system isbacked up from its present position (established by the X- andY-registers connected to the amplifiers I7 and 18) in a directionopposite that of the line to be displayed. The backup voltage is provided by the ramp generator in response to a control signal VIP which isdriven true (positive) to turn the transistor Q, on, and thereby drivean output terminal 34 negative to about l.2 volts determined by thebase-emitter drops 9 n transistors Q and Q Thereafter, when the controlsignal VIP is driven false, the transistor Q, is turned off and theintegrating capacitors start to charge up. When the ramp voltage passesthrough zero, an analog comparator 35 (FIG. 1) produces a signal VIZ toinitiate beam unblanking. Thus the ramp voltage is multiplied by scaledAX and AY in the MDACs and applied to summing amplifiers l7 and 1% whichprovide the X and Y deflection of the electron beam in the rightdirection. This allows the difference in velocity between the input andthe output of the deflection system to approach zero while the rampvoltage is increasing from 1.2 to 0 volts.

when the ramp voltage reaches zero, the signal VIZ sets a video-onsignal VII) in a beam control unit 50. The leading edge of the VIDtriggers a monostable multivibrator in that unit to produce a pulse LVDwhich delays turning the blanking signal of the CRT off (i.e. delaysallowing the beam to pass onto the CRT face) for an appropriate period.This delay adjusts for a fixed time error or lag of the beam behind thedeflection signals from the amplifiers l7 and 118. Thus, the backupfeature of starting the ramp voltage at 1.2 volts overcomes teardroppingand bending in the line due to an initially low beam velocity, and oncethe beam is up to an appropriate velocity (when ramp voltage is zero)the actual display of the line is delayed a fixed time to allow for thelag of the electron beam behind the deflection signals.

When the ramp voltage reaches a predetermined level the comparator 35generates a signal which resets the signal VID. The trailing edge of theVID signal then triggers a monostable multivibrator which produces apulse TVD that delays turning the blanking signal of the CRT back on foran appropriate period equal to or greater than the pulse LVD. Thisallows the lagging electron beam to reach the proper termination pointon the CRT face before the line drawing operation is ter minated. Theexact delay required at each end of a line drawing operation can bedetermined for a particular CRT by simple experimentation using variablemultivibrators. However, if the AX and AY data applied to the MDACs havebeen scaled, the time at which the comparator 35 generates a signal toset the signal VID must be scaled accordingly.

To terminate the line at the correct point when no scaling has beenintroduced, the comparator 35 detects when the ramp voltage reaches areference voltage of, for example 10 volts. When scaling has beenintroduced, it will be recalled that the AX and AY data were multipliedby 8 or 64 upon transfer of that data from the registers I0 and II inresponse to GTP and LTF signals, respectively. Therefore, to avoiddisplaying lines that are too long by a factor of 8 or 64, the referencevoltage of the comparator 35 is divided by a corresponding factor of l,8 or 64 to terminate the line being displayed when the ramp voltagereaches 1.0, 1.25 or 0.1565 volts according to whether the comparator 25transmits a GTE, GTF or LTF signal.

Rather than implement the comparator 35 with a variable referencevoltage, it is preferred to implement it with four separate differentialamplifiers, one with a zero reference voltage to transmit the VIZ signaland the remaining three with the reference voltages of IO, L25 and 0.l565 to transmit 1N0, [N1 and IN2 signals when the respective referencevoltages are reached. However, only the appropriate one of the signals1N0, [N1 and 1N2 is gated out to reset the signal VID in the controlunit 50 in response to the output signals GTE, GTF and LTF from thecomparator 25. Thus, the comparator 35 is scaled down to compensate forany scaling up of AX and AY data in the MDACs. As noted hereinbefore,this scaling technique reduces the required ramp rate range of the rampgenerator 21 by a factor of more than 100. The net result is moreefficient and effective beam velocity control through ramp ratevariation.

A preferred embodiment of a multiplying digital-to-analog converter isillustrated by the MDAC 22 in FIG. 3. However, it should be understoodthat any multiplying digital-to-analog converter may be employed. Thefunction of an MDAC is to provide an output voltage that is at all timesthe ramp voltage times a digital input. The conversion is accomplishedby a conventional R-ZR-typc ladder network 37, where each leg of theladder is connected either to ground through bus 38 or the ramp voltagethrough a bus 39. This connection is made by circuit, such as a circuit40 in the most significant bit position, comprising a storage flip-flop(that may be a .l-K type but shown as a D-type) and a pair offield-effect transistors (or other suitable switches). Each transistoris driven by a different side of the flip-flop to connect the associatedleg of the ladder 37 either to ground if the digit (most significantdigit for circuit 40) is zero or to the ramp voltage if the digit isequal to one.

The operational amplifier 36 inverts the output ramp from the ladder 37.Accordingly, it is connected to a negative output terminal NDX by a gate41 in response to a negative signal for the AX component as representedby a signal VGT. AXN derived from false output terminal of the sign bitposition of the AX register and VGT. The gate 41 is preferably aP-channel FET which requires a positive level to turn it off. The outputof the operational amplifier 36 is also connected to a secondoperational amplifier through a summing resistor 43 equal to thefeedback resistor 44 of the amplifier. In that manner, a positive rampis transmitted through a gate 45 when the sign of the AX component ispositive as represented by a signal VGT. AXP derived from the trueoutput terminal of the sign bit position and VGT.

Scaling the AX component is preferably accomplished by gating into thecircuits of the MDAC 22 the AX digits directly if GTE is true toplacethe most significant digit AX into the circuit 40, and all of the otherdigits of successively lower significance into successive circuits tothe right of the circuit 40. If GTF is true, the scaling factor is 8, sothe fourth most significant digit AX, is placed in the circuit 40. Allother digits of successively lower significance are placed intosuccessive circuits to the right with zeros in the last four circuits onthe far right. Similarly, if LTF is true, the scaling factor is 64, sothe AX component must be entered into the MDAC 22 effectively shiftedsix binary places to the left with the fourth most significant digit inthe circuit 40 and zeros in the six least significant bit positions. ANDgates 46, 47 and 48 and an OR gate 49 illustrate scaling by shifting"for the most significant bit position (circuit 40) of the MDAC 22, andsimilar gates 50 to 53 illustrate corresponding scaling operations forthe least significant bit position where the voltage input B to ANDgates 51 and 52 is the voltage level selected to represent binary 0. Forpositive logic gates, a binary l is typically represented by +3 voltsand a binary by circuit ground potential. Accordingly, for positivelogic gates the B-input terminals of gates 51 and 52 would be connectedto circuit ground.

Once the appropriate one of the gates 41 and 45 has been selected inaccordance with the sign of the AX compon h and the ramp generator hasbeen turned on by the signal VIP being driven false from +3 volts tozero to turn gate 30 of FIG. 2 on, the line drawing operation isinitiated. The comparator 35 then triggers a monostable multivibratorRET (FIG. 4) which on its trailing edge resets VGT to drive VIP true.That turns gate 30 off and thereby terminates the ramp voltagegeneration. After a fixed delay, the beam is also turned off byresetting flip-flop VIDD (FIG. 4) to allow the CRT blanking signal tocome back on.

A beam control network 56 (FIG. ll) adapted to turn the video beam offand on by setting and resetting (turning on and off) VIDD will now bedescribed with reference to FIG. 4, but it should be understood thatsuch a control network may be implemented in other ways, and may requiremodification to meet particular environments and operating requirementsof a system in which the present invention is used. At the same time,operation will be summarized for a complete line display cycle.

The asynchronous steps of one display cycle can be broken down into thefollowing (once the AX and AY registers have been loaded into registersill and 112 under control of an external device such as a digitcomputer).

2. Make the necessary comparisons to generate the appropriate one of thescaling control signals GTE, GTP and LTF and load the MDACs with scaledcomponents AX and AV. Also select the signs of the ramp outputs inresponse to the signs of the components stored in the registers Ill andH2.

2. Compare the scaled components AX and AY in the MDAC registers, andgate L and S digits into the ramp voltage generator 21 for the ramp rateselection.

3. Set VGT in response to a START signal from the external device whichit transmits after it has loaded the registers and allowed time for thepreceding steps. VGT enables MDAC polarity selection and triggers on itsleading edge the monostable multivibrator BVT.

4. After a delay set by the monostable multivibrator BVT, the rampvoltage generator is turned on.

5. Turn on video when the ramp voltage crosses zero volts in response toa VIZ signal from the analog comparator 35.

6. Turn off video in response to which ever one of the signals GTE-IND,GTFINI and LTF'INZ is transmitted by the analog comparator 35 when theramp reaches the reference voltage specified by the scaling controlsignals.

7. Reset the flip-flop VGT and update present position data in the X-and Y-registers.

The foregoing steps are controlled by the beam control unit 50 inresponse to the START signal. An AND gate 51 locks out other STARTsignals until the entire sequence has been completed and the flip-flopVGT has been reset. The component data AX and AY may be entered intoregisters 11 and 12 at the same time the START signal is transmitted tothe AND gate Sll.

The true output of the flip-flop VGT and the false output of themonostable multivib tor BVT are combined in a NAND gate to drive thesignal VIP true (+3 volts) for the period of the monostablemutlivibrator BVT. When W is reset to zero, the ramp generator 21 isturned on. Once the ramp crosses zero, the leading edge of the signalVIZ sets a flip-flop VID which immediately triggers monostablemultivibrator LVD. The trailing edge of the output pulse from themonostable multivibrator LVD sets flip-flop VIDD to turn on the beam(i.e. initiate unblanking). Thereafter, when the ramp voltage reachesthe selected reference level, the flip-flop VID is reset through an ORgate 53. The step voltage at the false output of the flip-flop VIDtriggers monostable multivibrator TV!) and RVGT. The delay period of themultivibrator TVD is set equal to or greater than delay period of themultivibrator LVD. Thus by adjusting the delay periods of themultivibrators LVD and TVD, the lag of the deflection system iscompensated. At some time before, or after, the multivibrator TVDresets, the multivibrator RVGT resets to reset the flip-flop VGT,thereby completing an operation. The advantage ofadjusting the delay ofmultivibrator RVGT to something less than that of multivibrator TVD isthat the signal VGT can be used to signal the external control devicethat operation is almost complete so that the device can prepare totransmit new data while the current operation is being completed.

From the foregoing, it may be seen that applicant has invented a new andimproved line display system for use with CRTs and similar devices.Although a particular embodiment has been illustrated, and particulartechniques of implementation have been described, it should beappreciated that the invention is in no sense limited to that.Accordingly, it is not intended that the scope of the invention bedetermined by that, but rather by the breadth of the appended claims.

What we claim is: l. In apparatus for controlling a device to display astraight line from a present position to a new position, where saidpositions are defined digitally in a rectangular coordinate system, anda given point is displayed on the device in response to a pair ofdeflection signals proportional to rectangular coordinates of said givenpoint, the combination comprising:

means for converting present position data into first and second analogsignals proportional to present position coordinates X and Y;

means for generating a ramp signal;

means for multiplying said ramp signal by the coordinate differences AXand A! between said present position coordinates and new positioncoordinates to provide third and fourth analog signals; and

means for adding said third and fourth signals to said first and secondsignals to provide said pair of deflection signals.

2. The combination of claim 1 wherein said ramp signal generating meansincludes a plurality of capacitors which may be selected for integratingcurrent from a constant source including apparatus for making the ramprate of said ramp signal approximately inversely proportional to thelength of a given line to be displayed by selecting combinations of saidcapacitors comprising:

means for determining which of the differences AX and AY is larger, andselecting the larger as a value L in digital form and the other as avalue S in digital form; means for forming a composite group of digitalsignals by combining with one group of digital signals of said value L,another group of digital signals of said value 8; and

means for selecting said capacitors in response to said composite groupof digital signals, where each of said capacitors selected by a digitalsignal of said one group of digital signals of said value L is weightedin proportion to the numerical weight of the digital signal by which itis selected, and each of said capacitors selected by a digital signal ofsaid other group of digital signals of said value S is weighted inproportion to approximately 0.375 the numerical weight of the digitalsignal by which it is selected, thereby maintaining the rate of changeof said pair of deflection said pair substantially constant.

' differences AX and AY.

4. The combination of claim 3 including control means for rendering saiddevice responsive to said deflection signals as said ramp signal startsto increase from zero volts, and means for terminating the response ofsaid device when said ramp reaches a predetermined level.

5. The combination of claim 4 including means for scaling saidpredetermined level by the reciprocal of a factor by which saiddifferences AX and AY are scaled for said given line to be displayed.

6. The combination of claim 5 wherein said device employs an electronbeam deflection system to display a line in response to said deflectionsignals, and said control means comprises means for delaying the turningon of said beam for a predetermined time while said ramp signalincreases from zero, and means for delaying the turning off of said beamfor a predetermined time after said signal reaches said predeterminedlevel, thereby compensating for lag in the response of said deflectionsystem to said deflection signals.

7. The combination of claim 6 including means for initiating said rampsignal at a level below zero.

8. The combination of claim 7 including means for selectively invertingsaid third and fourth analog signals for negative differences incomponents AX and AY, respectively before said third and fourth signalsare added to said first and second signals to provide said pair ofdeflection signals.

9. The combination ofclaim 1 including:

means for sealing the coordinate differences AX and AY to assure that atleast one of the differences will be equal to or greater than apredetermined number;

means for determining the approximate length of a line defined by saidscaled differences, and in response thereto for making the ramp rate ofsaid signal inversely proportional to said approximate length;

first control means for rendering said device responsive to saiddeflection signals when said ramp signal starts to increase from zerovolts;

second control means for terminating the response of said device whensaid ramp reaches a predetermined level; and

means for scaling said predetermined level by the reciprocal of a factorby which said differences AX and AY are scaled.

10. The combination of claim 9 wherein said devices employs an electronbeam deflection system to display a line in response to said deflectionsignals, including means for initiating said ramp signal at a levelbelow zero.

11. The combination of claim 10 including:

means for delaying said first control means in rendering said deviceresponsive for a predetermined period; and

means for delaying said second control means in terminating the responseof said device for a predetermined period;

thereby compensating for lag in the response of said deflection systemto said deflection signals.

1. In apparatus for controlling a device to display a straight line froma present position to a new position, where said positions are defineddigitally in a rectangular coordinate system, and a given point isdisplayed on the device in response to a pair of deflection signalsproportional to rectangular coordinates of said given point, thecombination comprising: means for converting present position data intofirst and second analog signals proportional to present positioncoordinates X and Y; means for generating a ramp signal; means formultiplying said ramp signal by the coordinate differences Delta X andDelta Y between said present position coordinates and new positioncoordinates to provide third and fourth analog signals; and means foradding said third and fourth signals to said first and second signals toprovide said pair of deflection signals.
 2. The combination of claim 1wherein said ramp signal generating means includes a plurality ofcapacitors which may be selected for integrating current from a constantsource including apparatus for making the ramp rate of said ramp signalapproximately inversely proportional to the length of a given line to bedisplayed by selecting combinations of said capacitors comprising: meansfor determining which of the differences Delta X and Delta Y is larger,and selecting the larger as a value L in digital form and the other as avalue S in digital form; means for forming a composite group of digitalsignals by combining with one group of digital signals of said value L,another group of digital signals of said value S; and means forselecting said capacitors in response to said composite group of digitalsignals, where each of said capacitors selected by a digital signal ofsaid one group of digital signals of said value L is weighted inproportion to the numerical weight of the digital signal by which it isselected, and each of said capacitors selected by a digital signal ofsaid other group of digital signals of said value S is weighted inproportion to approximately 0.375 the numerical weight of the digitalsignal by which it is selected, thereby maintaining the rate of changeof said pair of deflection said pair substantially constant.
 3. Thecombination of claim 2 including means for scaling the coordinatedifferences Delta X and Delta Y before forming said composite group ofdigital signals, thereby sealing said ramp rate in proportion to sealingof said coordinate differences to reduce the range of ramp ratesrequired for a given range of differences Delta X and Delta Y.
 4. Thecombination of claim 3 including control Means for rendering said deviceresponsive to said deflection signals as said ramp signal starts toincrease from zero volts, and means for terminating the response of saiddevice when said ramp reaches a predetermined level.
 5. The combinationof claim 4 including means for scaling said predetermined level by thereciprocal of a factor by which said differences Delta X and Delta Y arescaled for said given line to be displayed.
 6. The combination of claim5 wherein said device employs an electron beam deflection system todisplay a line in response to said deflection signals, and said controlmeans comprises means for delaying the turning on of said beam for apredetermined time while said ramp signal increases from zero, and meansfor delaying the turning off of said beam for a predetermined time aftersaid signal reaches said predetermined level, thereby compensating forlag in the response of said deflection system to said deflectionsignals.
 7. The combination of claim 6 including means for initiatingsaid ramp signal at a level below zero.
 8. The combination of claim 7including means for selectively inverting said third and fourth analogsignals for negative differences in components Delta X and Delta Y,respectively before said third and fourth signals are added to saidfirst and second signals to provide said pair of deflection signals. 9.The combination of claim 1 including: means for scaling the coordinatedifferences Delta X and Delta Y to assure that at least one of thedifferences will be equal to or greater than a predetermined number;means for determining the approximate length of a line defined by saidscaled differences, and in response thereto for making the ramp rate ofsaid signal inversely proportional to said approximate length; firstcontrol means for rendering said device responsive to said deflectionsignals when said ramp signal starts to increase from zero volts; secondcontrol means for terminating the response of said device when said rampreaches a predetermined level; and means for scaling said predeterminedlevel by the reciprocal of a factor by which said differences Delta Xand Delta Y are scaled.
 10. The combination of claim 9 wherein saiddevices employs an electron beam deflection system to display a line inresponse to said deflection signals, including means for initiating saidramp signal at a level below zero.
 11. The combination of claim 10including: means for delaying said first control means in rendering saiddevice responsive for a predetermined period; and means for delayingsaid second control means in terminating the response of said device fora predetermined period; thereby compensating for lag in the response ofsaid deflection system to said deflection signals.